Reliable Enumeration of CY7C656xx Hub with Reset Consideration | Cypress Semiconductor
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Reliable Enumeration of CY7C656xx Hub with Reset Consideration
What kind of situation CY7C656xx does not enumerate with the default descriptor?
The RESET must have at least the 2 msec after you get valid power. This issue here is to not use an RC network in this type of design. The reason deals with the fact that if you get other power sources on or partly on they leak into the chip and charge the capacitor. This kills the reset. So having a signal which is a dock reset or a reset that is applied whenever the 3.3 volts on the chip is not valid works best. The issue is not so much problems between the VBUSPOWER and the RESET it is a problem of not getting a reset because the design leaks voltages and charges caps. So, if you use a driven reset and it comes after you get valid power on the chip and it is applied for the 2 msec or longer everything should work right.
If the RC circuit is slower than the turn on time then there is a chance that the reset will never be seen because it will rise along with the power up of the part. A correct power on sequence will have the part get stable power then ~10mS later the reset line will go high. So the final RC fvalues depend on the regulator used.