Reducing the Deep-Sleep Current for PSoC® 4 Devices - KBA90930 | Cypress Semiconductor
Support & Community
Reducing the Deep-Sleep Current for PSoC® 4 Devices - KBA90930
How do I reduce the current consumption in PSoC® 4 devices in deep-sleep mode?
PSoC 4 devices consume about 1.5 mA in deep-sleep mode when measured in CY8CKIT-042. This behavior is observed only when the debug select option in system tab of Project_name.cydwr file is selected to “SWD” as shown in the following figure.
For a PSoC 4 project, when the debug select option is chosen to “SWD”, the drive mode of SWD pins is configured as Strong drive. This is the reason for the high current consumption even in deep-sleep mode. To reduce the deep-sleep current, you should manually change the drive mode of the SWD pins of PSoC4 device (i.e. P3 and P3 pins) to Analog Hi-Z mode before entering deep-sleep.
You can restore the original drive mode of the SWD pins once the device wakes up from deep-sleep. This method is only required if debugging is needed during deep-sleep. If not, the easiest method is to change debug select option from SWD to GPIO.
To change the drive mode of SWD pins to Analog Hi-Z, write the value zero to bits [6:11] of the PRT3_PC register present at the address 0x40040308. Writing zero to these bits of the PRT3_PC register sets the drive mode of SWD pins to Analog Hi-Z. For more details of PRT3_PC register, refer to PRT_PC register description in section 8.1.3 of PSoC 4 Registers TRM. The code snippet to change the drive mode of the SWD pins to Hi-Z before entering sleep mode and restore the drive mode of the SWD pins once the device wakes-up from Deep Sleep mode is given below: