Recommended Procedure for Updating CY22150 Registers | Cypress Semiconductor
Support & Community
Recommended Procedure for Updating CY22150 Registers
What is the recommended procedure for updating the registers (0x40, 0x41, 0x42) in the CY22150 that affect the PLL settings?
Here is a list of steps for dynamic updating with the CY22150.
1. Disable the clock outputs by turning them off through address 09H CLKOE bit settings or switch to the reference through the cross point switch matrix control at 44H-46H.
2. Reprogram the P, Q, charge pump and divider settings located at 40H-42H, 0CH, and 47H.
3. Enable the clock outputs through 09H or change the output clock reference in the cross point switch matrix at 44H-46H.
The reason for switching the clock outputs either off or to the reference is that the serial programming bits go into effect right after the acknowledge pulse is sent. Since the P and Q values are stretched out over 3 bytes (40H-42H), the PLL could go into an illegal state and output an unusable signal.