Receive Status Bits in HOTLink II | Cypress Semiconductor
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Receive Status Bits in HOTLink II
What is the purpose of receive status bits in HOTLink II? What is the function of priority in table 20 of the data sheet of CYP15G0401DXB? What are the different modes of status reporting?
At the HOTLink II receiver, when the 10B/8B Decoder is enabled (DECMODE not equal to LOW), each character presented at the Output Register includes three associated status bits RXST[2:0]. The purpose of the receive status bits is to identify:
2. The type of character present.
3. The state of receive BIST operations (regardless of the state of DECMODE)
These conditions normally overlap; e.g., a valid data character received with incorrect running disparity is not reported as a valid data character. It is instead reported as a Decoder violation of some specific type. This implies a hierarchy or priority level to the various status bit combinations. The priority levels determine the output of status bits when there are two conditions overlapping. In the case of overlapping conditions, the condition with the highest priority is on the output the receive status bits RXSTx[2:0]. For example, if there is an overlapping condition of loss of sync which is priority # 1 with any other condition, then the RXSTx[2:0] status pins will output status bits corresponding to loss of sync as it has the higher priority.
The priority levels of each status is listed in Table 20, when channel bonding enabled, and in Table 21, when channel bonding is disabled. Within these status codes, there are three modes of status reporting. The two data status reporting modes (Type A and Type B) are selectable through the RXMODE input. These status types allow compatibility with legacy systems, while allowing full reporting in new systems. These status values are generated in part by the Receive Synchronization State Machine, and are listed in Table 20. The receive status, when the channels are operated independently with channel bonding disabled, is shown in Table 21. The receive status, when Receive BIST is enabled, is shown in Table 22.