Reading a verilog component implemented in PSoC 3/5 PLDs by CPU/DMA | Cypress Semiconductor
Support & Community
Reading a verilog component implemented in PSoC 3/5 PLDs by CPU/DMA
How can CPU/DMA read from a verilog component implemented in PLDs of UDB Blocks.
There are no hardware registers associated with the PLD based verilog component which would store the values of the signals used inside the component. Hence the CPU/DMA cannot read directly from the component. One way to read from the component is to bring the required signals out through output pins and connect a status register to it.
A simple example of a 3 bit counter is as follows.
module Mod3Counter (
output [2:0] count;
//`#start body` -- edit after this line, do not edit this line
reg [2:0] count;
always @(posedge clock)
count <= count+1'd1;
// Your code goes here
//`#end` -- edit above this line, do not edit this line
As it can be seen ‘count’ has been made an output signal. A status register should be connected to the ‘count’ terminal as shown below.
The CPU can read the counts by simply reading the status register. The counts can be transferred to another destination using DMA by setting the source address as the address of the status register.