Read-Back of Internal Address Counters for synchronous dual port SRAM's | Cypress Semiconductor
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Read-Back of Internal Address Counters for synchronous dual port SRAM's
- How can one see the current state of the internal counter?
- Is there a way to check the state the burst counter?
- Is address readback different for the CY7C08x1V / CY7C08x2V devices?
All Cypress synchronous dual-ports come with internal counters (except CY7C0853V). One of the added features that comes with internal counters is that the value in the registers can be read back out. However, the way this is done is different for the CY7C09xxx(V) family of synchronous dual-ports and the CY7C08x1V / CY7C08x2V family of dual-ports. Below is a description of both families:
CY7C09xxx(V): In these dual-ports, the internal address counter is read out onto the I/O lines. Depending on the depth of the device, the number of I/O's used will differ. Most times, though, only the most significant bits of the I/O bus will be used. For example, the CY7C09569V is a 16K x 36 dual-port. It is addressed by 14 address bits A[13:0]. These are read out only on the most significant bits. Since there are only 14 address bits to read out, it is read out only from IO[17:4]. The request for address readback is: OE# = L, R/W# = H, ADS# = L, CNTEN# = H, CNTRST# = H
CY7C08x1V / CY7C08x2V: In these dual-ports, the internal address counter is read out onto the address lines. So this family of dual-ports has bi-directional address and data lines. Because they are evenly matched, the number of bits in the address counter are the same number of bits in the address bus. The request for address readback is: CNT/MSK# = H, CNTRST# = H, ADS# = L, CNTEN# = H