Race condition of the flags in asynchronous FIFO's | Cypress Semiconductor
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Race condition of the flags in asynchronous FIFO's
- Why does my /EF seem to oscillate between high and low very frequently?
- Why does it seem like my /FF is flickering?
It's common to encounter race conditions when operating the FIFO at the boundary. Referring to the switching waveform for "Empty Flag and Read Data Flow-Through Mode" in the data sheets of certain asynchronous FIFO's, notice that when there is only ONE word in the FIFO, the falling edge of /R will cause /EF to get asserted, while the rising edge of /W will cause /EF to de-assert. Thus, if these two edges are too close to one another, a "race condition" will occur, where /EF will not truly reflect the state of the FIFO for a short period of time.
That's part of the reason why newer generation FIFOs have programmable flags, which signals the write and read interfaces when the FIFO is almost full or almost empty, so as to avoid such boundary condition. More information regarding this race condition is described in detail in the application note "Understanding Large FIFO's" (Understanding Large FIFO's App Note).