QDRII/DDRII/QDRII+/DDRII+ clocking | Cypress Semiconductor
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How should be QDRII/DDRII/QDRII+/DDRII+ clocking ?
All QDR-II, QDR-II+, DDR-II, and DDR-II+ devices require an input clock pair, K and K# while All QDR-II and DDR-II devices have an output data clock pair, C and C#. These clocks can be optionally used to control when the output data emerges from the device. This is very useful in systems in which multiple SRAMs are located at different physical distances from the bus master. All output data can be aligned using C and C# such that the whole result can be captured and easily synchronized at the bus master simultaneously. All QDR-II, QDR-II+, DDR-II, and DDR-II+ devices have optional-use output echo clocks CQ and CQ#. The echo clocks are source synchronous with the data and must be delayed to capture data at the receiver.
All these clocks are complementary, complies with HSTL Class I I/O standard and are non differential (single ended)