QDR Clock modes | Cypress Semiconductor
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QDR Clock modes
What is the significance of having two clock signals K and /K? Also, what is the need for the clock signals C and /C?
Response: The clocks K and /K are tied to the core functionality of QDR. Both clocks are single ended signals. All control signals are latched only on the rising edge of K in the case of both burst of 2 and burst of 4 devices. For burst of 2 devices, write address is latched on the rising edge of /K and read address is latched on the rising edge of K. In a burst of 4 device, both write and read addresses are latched only on the rising edge of K. Data in and Data out are associated with both the rising edges of K and /K on burst of 2 and 4 as well.
/K bar is typically 180 degrees out of phase with respect to K. This effect produces the ability for the QDR to perform a write and read in one clock cycle. C and /C are also input clocks, which when provided, controls the outputs, i.e. only the outputs are associated. If the customer wishes not to use these clocks, then these need to be tied to a 'Vdd' wherein K and /K will be used to reference the outputs.
C and /C can be used in a situation where multiple QDR SRAMs are cascaded together. C and /C can be used to synchronize outputs from all the multiple QDR SRAMs that can get skewed due to trace delays. Refer to the Application example in the datasheet for further clarification.