PSoC I2C Block Clock Stretching: Worst Case Duration | Cypress Semiconductor
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PSoC I2C Block Clock Stretching: Worst Case Duration
Question: What is the worst case duration of clock stretching?
Answer: Clock stretching is a phenomenon where the PSoC I2C slave pulls the SCL line low after the 8th clock of every I2C data/address transfer (before the ACK/NAK stage).
PSoC when configured to act as an I2C slave pulls the SCL line low soon after the reception of an incoming I2C data byte. An interrupt is accompanied with this event and it is inside the ISR of this interrupt that CPU initiates the release of the clock line by writing appropriate ACK/NAK status to I2C control register.
Worst case time for which the clock stretching occurs can be computed from the equation below,
No of enabled interrupts in the project = N (including the I2C ISR)Clock Stretching Time = (25Cycles * N) * CPU_CLK + (Sum of execution time of N ISR’s) Note: Execution time of one ISR can be computed by multiplying CPU clock time with number of CPU clock cycles associated with that ISR