PSoC® 4 System Clock Configuration for 1-MSPS SAR ADC Sample Rate - KBA87092 | Cypress Semiconductor
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PSoC® 4 System Clock Configuration for 1-MSPS SAR ADC Sample Rate - KBA87092
How should I configure the PSoC 4 system clock to get a SAR ADC sample rate of 1 MSPS?
To get a sample rate of 1 MSPS at 12-bit resolution, the PSoC 4 SARADC must work at 18 MHz. The SAR ADC clock has a special requirement; it can only use the integral frequency divider because the fractional frequency divider is not suitable.
Thus, to get a 1-MSPS sample rate, you must set the internal main oscillator (IMO) frequency at 36 MHz. Open the Clocks tab in cydwr and click Edit Clock to set the IMO at 36 MHz, as shown in the following figure.
Figure 1. IMO Frequency Setup for 1 MSPS SAR Sample rate