PSoC® 4 SAR ADC Configurable Sample Time - KBA87493 | Cypress Semiconductor
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PSoC® 4 SAR ADC Configurable Sample Time - KBA87493
What is the SAR ADC configurable sample time (acquisition time) in PSoC 4?
The sample time is defined as the time cost by the sample-and-hold (S/H) circuit inside SAR ADC. To accommodate signals with varying source impedances and frequencies, PSoC 4 SAR ADC supports a programmable sample time. To make this capability available across multiple channels without slowing them down collectively to the slowest common denominator, the SARSEQ has up to four fully programmable 10-bit sample-time options. These options allow the sample time to be configurable from 2 to 1023 SAR ADC clocks.
In PSoC Creator™, every channel can choose sample time (called acquisition time in PSoC Creator) from one of four options: A clks, B clks, C clks, and D clks (see Figure 1).
The minimum acquisition time of each ADC channel depends on the channel’s serial resistance and sample capacitance. Refer to the “SAR ADC Acquisition Time” section of AN88619 for details on the acquisition time calculation.
Figure 1. Sample-Time Setup in PSoC Creator