PSoC 3 Boot/Startup Procedure | Cypress Semiconductor
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PSoC 3 Boot/Startup Procedure
What happens during the boot process of PSoC 3?
PSoC3 startup / boot procedure can be divided into two major phases.
1. Hardware Startup - Hardware startup begins after RESET is deasserted. In case of power up, this phase begins after voltages are ramped up. During hardware startup, first phase is reset phase where PSoC is inactive and waiting for resources to get stabilized enough to enter the next phase called boot phase. At the beginning of boot phase, internal main oscillator (IMO) is started based on partially stable reference. This IMO clocks the device. A dedicated hardware state machine then control basic configuration and trim values using direct memory access (DMA). At the end of hardware start phase, internal reference gets stable, partially trimmed IMO is configured based on CFGSPEED bits of non volatile latch (NVL), master clock is active which uses IMO directly, and I/Os are configured as per other NVL settings. During the whole hardware startup phase, CPU is not active.
2. Firmware Startup - At the beginning of firmware startup, CPU starts it's operation from 0x0000 location in flash. The firmware startup takes care of default settings of analog and digital blocks, internal routing of signals, clock tree, debug circuitry and DMAs as per the PSoC Creator project. The whole code for firmware startup is present in cyfitter_cfg.c and KeilStart.a51 files.
The Application Note AN60616 - PSoC® 3 Startup procedure covers this in more details.