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Programming Modes Supported in a 48-Pin PSoC® 3 Device – KBA94456 | Cypress Semiconductor

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Programming Modes Supported in a 48-Pin PSoC® 3 Device – KBA94456

Last Updated: October 31, 2014

What programming modes are supported in a 48-pin PSoC® 3 device?


48-Pin PSoC 3 Parts can be programmed using Power Cycle programming mode and Reset programming mode. In Power Cycle mode, the host programmer toggles power to the PSoC 3 power supply pins (VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, and VDDIO3) to cause a device reset.

The device can be programmed using Reset programming mode as well. On 48-pin package parts, the external reset (XRES) is shared with port pin P1[2]. These parts do not have a dedicated XRES pin. To program the device in Reset mode, the device must be reset by toggling P1[2]. For these parts to be programmed in Reset mode, the Use Optional XRES option must be checked in the .cydwr settings as shown in Figure 1.

Figure 1. Enabling the Optional XRES in the .cydwr file


When the optional XRES pin (P1[2]) in 48-pin parts is configured as a GPIO Pin, the only way for the host programmer to do a device reset is to toggle power to the PSoC 3. This is because there is no dedicated XRES pin in 48-pin parts, unlike the other pin-count packages. Note that the 48-pin parts coming from the factory have the P1[2] pin configured as XRES by default. Disabling P1[2] as XRES for 48-pin parts is only done by the user. If the user programs a hex file that disables P1[2] as XRES, then the XRES method is not available for subsequent programming and the power cycle method must be used. The power cycle method is complex compared to the XRES method because it requires special hardware design considerations for power toggling.

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