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Power Up Timing Sequence for FX2LP18 | Cypress Semiconductor

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Power Up Timing Sequence for FX2LP18

Last Updated: June 23, 2011

Is there a specific power up timing sequence that FX2LP18 need to adhere to for proper operation?


There are no power sequencing requirements on analog and digital supplies(AVCC and VDD) for FX2LP18. Just the Reset timing requirements as stated in the datasheet are required. Requirement on reset is stringent since FX2LP18 requires the specified reset time to lock the PLL for the USB PHY clock(480MHz).

When a crystal is used with the CY7C68053, the reset period must allow for the stabilization of the crystal and the PLL. This reset period must be approximately 5 ms after VCC has reached 3.0V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 μs after VCC has reached 3.0V. If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200 μs. Please read through section 3.9 "Reset and Wakeup" of the FX2LP18 datasheet to read in detail about the reset requirements of FX2LP18.

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