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Power-On-Reset Triggering | Cypress Semiconductor

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Power-On-Reset Triggering

Last Updated: August 30, 2010

Question: What is the minimum pulse width on the VDD line to trigger the POR? Is it just an edge detection?

Response: There is no specification for the minimum time VDD has to go low to trigger POR. The moment VDD drops below the POR threshold , the Reset will be triggered.

The Voltage Monitor Control Register (VLT_CR) is used to set the trip points for POR, LVD, and the supply pump as mentioned in Section 32 of the Technical Reference Manual.

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