Power down requirements for the CY8C20xx6A, CY8CTMGxxx, CY8CTMAxxx, CY8CTSTxxx, CY7C643xx and CY7C604xx devices | Cypress Semiconductor
Support & Community
Power down requirements for the CY8C20xx6A, CY8CTMGxxx, CY8CTMAxxx, CY8CTSTxxx, CY7C643xx and CY7C604xx devices
Are there any power down requirements for the CY8C20xx6, CY8C20xx6A, CY8CTMGxxx, CY8CTMAxxx, CY8CTSTxxx, CY7C643xx and CY7C604xx devices ?
Yes, the devices have the following power-down requirements:
If powering down in standby sleep mode, to properly detect and recover from a V_DD brown out condition any of the following actions must be taken
• Ensure that VDD falls below 100mV before powering back up.
• Bring the device out of sleep before powering down.
• Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
• Increase the buzz rate to ensure that the falling edge of V_DD will be captured. The rate is configured through the PSSDC bits in the SLP_CFG register.
For the referenced registers refer to the Technical Reference Manual. In deep sleep mode, additional low-power voltage monitoring circuitry allows V_DD brown out conditions to be detected. For edge rates slower than 1V/ms, these requirements are not necessary in deep sleep mode.