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POR and LVD settings are different | Cypress Semiconductor

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POR and LVD settings are different

Last Updated: December 17, 2009

Question Is the POR setting based on the LVD selection made in Global parameters?

Response No. The Low Voltage Detect (LVD) value is selected in the PSoC Designer global settings, but this is not related to the Power on Reset (POR) level. The LVD only gives an interrupt and does not reset the chip.

The POR level gets set based on the CPU clock frequency and Vdd setting. If the Vdd dips below the POR value, the chip resets. Refer to KB article “POR setting based on CPU and Vdd”  for more details on the POR setting

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