You are here

POR and Boot routine timing | Cypress Semiconductor

Support & Community

POR and Boot routine timing

Last Updated: August 28, 2009

Question: What is the fastest time we can process a POR and Boot routine?


1) The POR signal is asserted until the IPOR Trip voltage is reached.

2) The PSoC enters an acquire mode where it waits for a key. If it receives the key, it enters test mode (hold-off).

3) The CPU boots by executing code in its internal Supervisor ROM (SROM).

4) The Boot.asm code and User code is executed .

Times for 27xxx and 24xxx:

Hold-off*: 16ms (512 ILO cycles at 32kHz)

SROM: 2.2ms(6579 CPU cycles at 3MHz CPU)

Total: approximately 18ms

Time for 29xxx:

Hold-off*: 16ms (512 ILO cycles at 32kHz)

SROM: 2.2ms(6586 CPU cycles at 3MHz CPU)

Total: approximately 18ms

*The Hold-off time is based on 512 cycles of the ILO. At this stage in the boot process, the ILO is untrimmed. Since the ILO trimmed has an accuracy of 50%, the hold-off time can vary considerably.

To speed this time up using external parts:

A capacitor, connected to the XRES pin, can be tied to the VDD signal in series with a resistor (See attached schematic). All power supplies vary, so make sure to choose a capacitor value that will reach the VIH levels according to the specification of the part. If the XRES peak is too low, then choose a larger capacitor.

Typical values may be a 1k ohm resistor in series with a .47uF capacitor.

Related Articles: XRES - What is the function of this pin? (21826)

Keywords: POR, Boot, Fastest, Time

File TitleLanguageFile SizeLast Updated
Download Schematic.rtfEnglish198.68 KB12/19/08

Provide feedback on this article

Browse KB By Product

Browse KB by Type