PLL Lock Time of CPLL in CY2291/CY2292 | Cypress Semiconductor
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PLL Lock Time of CPLL in CY2291/CY2292
Why does the CPLL on the CY2291 or CY2292 have a longer lock time than the UPLL or SPLL?
The CPLL has a slew limiter to smooth out frequency transitions when the select lines S2, S1 and S0 are changed. The slew rate for the CPLL is a min of 1MHz/ms to a max of 20MHz/ms as opposed to a 1ms lock time for the UPLL and SPLL.