Pins v2.0 Pulled-Up and Pulled-Down POR Settings Show a Glitch at Power Up - KBA93531 | Cypress Semiconductor
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Pins v2.0 Pulled-Up and Pulled-Down POR Settings Show a Glitch at Power Up - KBA93531
When configuring the Power-On Reset properties of a port in PSoC® 3 and PSoC 5LP to either Pulled-Up or Pulled-Down, a glitch appears at the pin at power-up. How do you work around this issue?
The glitch appears in Pins v2.0 for PSoC 3 and PSoC 5LP due to a firmware bug that switches the Power-On Reset settings for Pulled-Up and Pulled-Down modes. The Component is not affected if it is set as Don't Care or High-Z Analog. If you wish to use the Pulled-Up or Pulled-Down POR settings, then choose one of the following workaround options:
- The preferred workaround is to downgrade to the Pins v1.90 Component in the design. This will allow you to configure the Power-On Reset state to Pulled-Up or Pulled-Down without any issues.
If you want to use Pins v2.0 in PSoC 3 and PSoC 5LP designs, then there are two options:
- Leave the Power-On Reset configuration as Don't Care, which is a high-impedance state, and use external pull-up or pull-down resistors.
- Flip the POR settings for Pulled-Up and Pulled-Down (i.e., select pull-up if you want pull-down, or vice-versa). However, if you upgrade to the Pins v2.10 Component, then you must undo this change.