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Pin Mapping Differences Between the EZ-BLE™ PSoC® Evaluation Board (CYBLE-214015- EVAL) and the BLE Pioneer Kit (CY8CKIT-042-BLE) - KBA216236 | Cypress Semiconductor

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Pin Mapping Differences Between the EZ-BLE™ PSoC® Evaluation Board (CYBLE-214015- EVAL) and the BLE Pioneer Kit (CY8CKIT-042-BLE) - KBA216236

Last Updated: October 18, 2016
Version: 
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Question: 

Are there differences between the pins exposed on J1 and J2 headers of the EZ-BLE PSoC Evaluation Board (CYBLE- 214015-EVAL) and the pins expected by the J10 and J11 headers on the BLE Pioneer Kit (CY8CKIT-042-BLE)

Answer: 

Yes, there are differences in pin mapping between exposed pins of EZ-BLE PSoC Evaluation Board and BLE Pioneer Kit. The EZ-BLE PSoC Evaluation Board quick start guide explains how to use the board with the BLE Pioneer Kit and the differences in pin mapping. This is also explained below. 

Figure 1 shows the J10 and J11 headers on the BLE Pioneer Kit. 

Figure 1: J10 and J11 headers on BLE Pioneer Kit

Figure 1: J10 and J11 headers on BLE Pioneer Kit

The EZ-BLE PSOC Evaluation Board can be plugged on to these headers as shown in Figure 2

Figure 2: EZ-BLE PSoC Evaluation Board plugged on BLE Pioneer Kit

Figure 2: EZ-BLE PSoC Evaluation Board plugged on BLE Pioneer Kit

Figure 3 shows the pinout and details of the EZ-BLE PSoC Evaluation Board (CYBLE-214015-EVAL), which is a fan-out board for the EZ-BLE PSoC Module (CYBLE-214015-01). 

Figure 3: EZ-BLE PSoC Evaluation Board (CYBLE-214015-EVAL) Pinout

Figure 3: EZ-BLE PSoC Evaluation Board (CYBLE-214015-EVAL) Pinout

The EZ-BLE PSoC Evaluation Board’s J2 and J1 are plugged in to J11 and J10 headers of BLE Pioneer Kit respectively. 

The EZ-BLE PSoC Module exposes a subset of the GPIOs that are expected on the BLE Pioneer Kit. Therefore, the evaluation board for the module has several pins that do not map to any port of the module. In addition, some pins exposed on the J1 and J2 headers of the evaluation board differ from the pins expected on the J10 and J11 headers of the BLE Pioneer Kit. A table showing the complete pin mapping and highlighting differences is shown below. The table specifies NC (No Connect) for the pins that are not available on the evaluation board.

CY8CKIT-042-BLE J11 Header CYBLE-214015-EVAL J2 Header   CY8CKIT-042-BLE J10 Header CYBLE-214015-EVAL J1 Header
VDDD VDD*   VDDA VDD*
VREF VREF   VDDR VDDR
XRES XRES   GND GND
GND GND   GND GND
P0_0 NC   P2_0 P0_1**
P0_1 NC**   P2_1 P2_1
P0_2 NC   P2_2 P2_2
P0_3 NC   P2_3 P2_3
P0_4 P0_4   P2_4 P2_4
P0_5 P0_5   P2_5 P2_5
P0_6 P0_6   P2_6 P2_6
P0_7 P0_7   P2_7 P3_5**
P1_0 P1_0   P3_0 P3_0
P1_1 P1_1   P3_1 P3_1
P1_2 P1_2   P3_2 P3_2
P1_3 P1_3   P3_3 P3_3
P1_4 P1_4   P3_4 P3_4
P1_5 P1_5   P3_5 P3_5
P1_6 NC   P3_6 P3_6
P1_7 NC   P3_7 P3_7
      P4_0 NC***
      P4_1 NC
      P5_0 NC
      P5_1 NC

*EZ-BLE PSoC Module shorts the digital and analog power rails of PSoC 4 BLE (highlighted rows in blue) 
**Pins differ from the pins expected on the BLE (highlighted rows in yellow)
***The EZ-BLE PSoC Module has the P4_0 pin however this is connected to the Cmod capacitor on the EZ-BLE PSoC Evaluation Board (and similarly P4_1 pin is connected to Ctank capacitor) and is not exposed on the J1 header.

Note: The EZ-BLE PSoC Module is supported on PSoC®CreatorTM 3.3 SP1and later versions. While the GPIOs available on the EZ-BLE PSoC Module and consequently on the EZ-BLE PSoC Evaluation Board are limited, every functionality available on a PSoC 4 BLE silicon is available on the EZ-BLE PSoC Module. The only exception is the CapSense® Gestures Component that handles one- and two-finger gestures. This Component is not available on the EZ-BLE PSoC Module.

Headers (on CYBLE-214015-EVAL): Usage description

Headers Usage description
J3

It is used to short VDDD and VDDR.

Note: J3 can be ignoredfor usage if customers insert CYBLE-214015-EVAL into CY8CKIT-042-BLEsince VDDD and VDDR are short in CY8CKIT-042-BLE. However, if customers use the CYBLE-214015-EVAL separately, customer need to short J3 based on application requirement.

J5

It is used to short VDDD and VDDA.

Note: J5 can be ignoredfor usage if customers insert CYBLE-214015-EVAL into CY8CKIT-042-BLEsince VDDD and VDDA are short in CY8CKIT-042-BLE. However, if customers use the CYBLE-214015-EVAL separately, customer need to short J5 based on application requirement.

J6

It is used to short P3.5 of CYBLE-214015-01 module to either/both of P3.5 and P2.7 of CY8CKIT-042-BLE

Applicable Kits:
EZ-BLE PSoC Evaluation Board PRoC BLE Modules PSoC 4 BLE Modules
CYBLE-214015-EVAL CY5671 CY5674 CY8CKIT-142 CY8CKIT-141
YES NO NO NO NO
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