Pin Definitions of Async SRAM's | Cypress Semiconductor
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Pin Definitions of Async SRAM's
What is the functionality of the different pins of Asynchronous SRAM's?
The functionality of the different pins of Asynchronous SRAM's are:
1. CE# (or CE1# and CE2) : Chip Enables (CE#, CE1#, CE2) are used for enabling /disabling the chip.
2. WE#: Write Enable (WE#) is used for enabling write operation in the SRAM
3. A0-An: represent the address pins
4. IO0-IOn: represent the IO (data) pins
5. OE# : Output Enable(OE#) is used for enabling or disabling the output buffer on all IO0-IO15 pins (for a x16 device) and IO0-IO7 pins (for a x8 device).
6. BHE# (for x16 device): Byte High Enable is used for enabling or disabling the IO buffers on IO8-IO15 pins.
7. BLE# (for x16 device): Byte Low Enable is used for enabling or disabling the IO buffers on IO0-IO7 pins.
8. VCC: Power pin
9. VSS: Typically, the ground pin
10. NC: These are the pins not connected to the die
11. DNU: These pins could be connected to the die, and should be left floating or tied to VSS (as specified in the datasheet)