Physical Interface and CPU Responsibilities for the SX2 | Cypress Semiconductor
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Physical Interface and CPU Responsibilities for the SX2
What physical interface is presented to the external master or CPU from the EZ-USB SX2? What is the external master or CPU responsible for?
The EZ-USB SX2 basically presents a Slave FIFO interface to the external master or CPU, complete with FIFO flags, status interrupts, etc. SX2 is an 'intelligent' USB 2.0 SIE-only device that handles the USB interface portion of the system. The external master is responsible for enumerating SX2, processing USB requests, and controlling the transfer of payload data.