PCB Design : Thermal Design Consideration for FX2LP QFN Package. | Cypress Semiconductor
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PCB Design : Thermal Design Consideration for FX2LP QFN Package.
What are the consideration for thermal efficient PCB design with EZ-USB FX2LP QFN Package?
The EZ-USB FX2LP QFN (Quad Flatpack No leads) is a package with a small footprint and low profile. It has excellent thermal properties: a very low Θja of approximately 25°C per watt. These thermal properties are ideal for the high-performance FX2LP.
The appropriate thermal design for use with the EZ-USB FX2LP is to dissipate heat from the QFN package by conduction, not convection. Heat is conducted away from the package through its bond to the PCB. From there it is dissipated into the signal ground plane. Special attention to the heat transfer area below the package is required.
On the bottom of the package is a metal pad referred to as the exposed die attach paddle, (or simply exposed paddle). The exposed paddle is the means by which most of the EZ-USB FX2LP thermal energy is dissipated away from the package. The exposed paddle is a square metal area approximately 6 mm on a side.
The design of the land area for the exposed paddle is critical to proper thermal transfer. A copper fill is to be designed into the PCB and under the QFN in order to assist thermal transfer. Figure 1 is the diagram of the PCB land area for the EZ-USB FX2LP.
Figure 1. Diagram of the PCB Land Area
The heat is transferred to the solid signal ground plane of the board. The connection is made using a 5 x 5 array of 25 plated through-holes in the PCB; each should have a finished diameter ranging from 12 mil to 13 mil. Solder mask is placed over the top of each plated through-hole to resist solder flow into the hole. The mask also is used to create voids in the flowed solder for out-gassing during the solder reflow process.
Research done by Amkor, a package manufacturer, has determined that an array of more than 16 and less than 36 plated through-holes should be used for the PCB land for the exposed paddle. Figure 2 shows the trend in Θja with respect to the number of vias. This specific graph show the trend on Amkor’s 7 mm 48-lead package. The result shows that the thermal efficiency improves with increase in the number of plated though holes. A lower Θja indicates a better thermal efficiency. The results obtained on the Amkor part can be extrapolated to the EZ-USB FX2LP.
Figure 2. Thermal Efficiency
Figure 3 shows the solder mask region at the package. Each of the 25 plated through-holes is in the center of each circle of solder mask. Black area indicates absence of solder mask.
Figure 3. Solder Mask
The signal ground plane provides the major area for thermal dissipation. Some developers may need a much smaller board size. To maximize area devoted to thermal dissipation, the designer should use the bottom layer of the PCB. This is in addition to the internal solid ground plane, (which must be kept to maintain proper signal impedance). The metal fill must be connected to the signal ground plane at each of the 25 plated through-holes under the QFN mounting. Additional 13-mil plated throughholes may be placed throughout the board to connect to the internal signal ground plane as desired. Most holes should be placed as close to the QFN package as practical to improve thermal transfer.
The enclosure for the circuit board assembly affects thermal performance. This article does not give a specific example of enclosure design. However, following the guidelines for PCB design described in this article will assure the most efficient method to conduct heat away from the QFN package without the use of heat sinks. A large, solid ground plane with no large gaps close to the QFN mounting area will efficiently conduct heat through the PCB.