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Overloading Issue When PGA in Attenuation Mode is Connected to SC block | Cypress Semiconductor

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Overloading Issue When PGA in Attenuation Mode is Connected to SC block

Last Updated: December 14, 2009

Question: I have configured a PGA in attenuation mode (Gain < 1).  When I connect the output of the PGA to an SC Block, the output of the PGA drops.  Why is this happening and what is the workaround?

Response: In PSoC1, when PGA is configured for gain less than 1 (attenuation), op-amp acts like a voltage follower and output of the OpAmp is fed to a Resistor matrix which acts as a potential divider.  If the output of this stage is connected to a low impedace load, the load acts in parallel with the lower end of the potential divider and will reduce the output voltage.

The input impedance of SC block is given by formula:

Rc = 1/(Fs*C)

Where Fs is Switching frequency and C is capacitor value.  This input imepdance of the SC Block will cause in a reduction in output voltage.

Following are some of the workarounds to resolve this issue:

1. Connect the output of the PGA to another PGA configured for unity gain.  The input impedance of the unity gain PGA is very high and will not load the Attenuator PGA.

2. Route the output of the Attenuator PGA to an output pin through the Analog bus and the Analog buffer. The Analog output buffer has a very high input impedance and hence will not load the PGA.  Now route back the output pin through another input pin to the SC Block.

3. As the input impedance of the SC Block depends on the Column clock and the input capacitance, reduce either the input capacitance, or the Column clock or both to increase the input impedance.  Though this will not completely remove the loading, it will reduce the effect.  Also, this method may work well where the gain of the PGA is farther from unity (the value of the lower end of the potential divider is low)

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