You are here

Output State for the FIFOs | Cypress Semiconductor

Support & Community

Output State for the FIFOs

Last Updated: June 17, 2011

- Can I make the data outputs (Q0 - Q8) to be normally high?
- What is the status of the data outputs after reset?
- What happens to the data outputs when /OE is asserted?


The Output Enable signal, OE#, is an asynchronous signal which controls the status of the data outputs of the FIFO (Q[0:8]).  When OE# is disabled (high), all the data outputs will be in a High Z (high-impedence) state.  When OE# is enabled (low), then the data outputs will be driven to a logic high or logic low value, depending on the value of the data being read out of the FIFO.

After a FIFO reset, if OE# is enabled, then the data lines will all go low tRSF after the assertion of the reset signal.

If there is a need for the data outputs to be driven logically high after reset, the only way to work around this behavior is to write a dummy character of all 1's into the FIFO and read that value out.  This will keep the data outputs high until the next character is read.

Knowledge Base Tags: 

Provide feedback on this article

Browse KB By Product

Browse KB by Type