Output Clocking Constraints questions for CY22388/89/91 | Cypress Semiconductor
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Output Clocking Constraints questions for CY22388/89/91
Clock H is a copy of clock D on the 20 and 32 pin packages. If the OE function is set for clock D, what will be the state of clock H when D is tri-sated?
Clock H will continue to run unless its OE function is set. <
Question: Clock H is a copy of clock D on the 20 and 32 pin packages. If the FS pin for Clock D is changed, does the output frequency on Clock H change?
Response: Yes, the output frequency on Clock H will follow clock D even if Clock D is tri-sated.
Question: There are 4 PLLs in this device. Does that mean that all of the clock outputs are unrelated in frequency?
Response: Only the frequencies that are derived from different PLLs are unrelated. Frequencies that are derived from the same PLL only differ in post divider values and are still related.
Question: There are 4 PLLs and eight outputs in this device. Can the outputs be derived from any PLL and or can the PLLs get their reference from another PLL?
Response: The factory configurable software has built in rules that govern the PLL and clock routing architecture.