Optimizing SPI bus transactions | Cypress Semiconductor
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Optimizing SPI bus transactions
Do you have any suggestions for optimizing SPI bus transactions?
The Receive ISR typically requires reading the Receive Interrupt Status, Receive Data and Receive Valid registers. These registers are consecutive allowing burst reads (using the auto-increment bit in the SPI address). Using the burst read method reduces the SPI transaction from six bytes to four (writing the address of the Receive Interrupt Status Register followed by reading the Receive Interrupt Status, Receive Data and Receive Valid). If the Valid Data bit is set in the Receive Interrupt Status Register all eight bits in the Receive Data are valid; therefore it is unnecessary to read the Receive Valid Register, reducing the SPI transaction to three bytes.