Operating EZI2C in PSoC at lower than 50KHz frequency | Cypress Semiconductor
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Operating EZI2C in PSoC at lower than 50KHz frequency
I want to operate PSoC EZI2C as a slave in I2C communication. The I2C master clock frequency is 40KHz, but in designer the options available for CLK are 50KHz, 100KHz and 400KHz. Can PSoC respond to 40KHz ?
As per the I2C spec, the I2C bus works at the speed of the slowest device on the bus. In this case the master CLK is slowest at 40KHz. So, if the master is sending data at a rate of 40KHz then the PSoC EzI2C will also respond at a rate of 40KHz. You can select EzI2C CLK frequency more that 40KHz i.e. 50KHz.
Note: The way EzI2C has been implemented in PSoC1, always set the EzI2C CLK frequency higher than the master CLK or else PSoC1 might not respond.