Occasional Corruption in Results of PSoC® 1 ADCINCVR/DUALADC/TRIADC – KBA88326 | Cypress Semiconductor
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Occasional Corruption in Results of PSoC® 1 ADCINCVR/DUALADC/TRIADC – KBA88326
The conversion results of PSoC® 1 ADCs such as ADCINCVR, DUALADC, and TRIADC sometimes show a large glitch (typically a negative spike), although the input voltage is stable. What causes this, and how do you overcome this issue?
The user modules such as ADCINCVR, DUALADC, and TRIADC generate the analog-to-digital conversion result by counting the digital bit stream sent out by the analog modulator over a fixed time interval.
The LSB of this counter (that counts the digital bit stream) is implemented as a digital block. But the MSB of this counter is implemented in firmware as a byte variable (to avoid the use of an additional digital block resource). This MSB value (byte variable) is incremented by 1 on each interrupt generated by the digital block that contains the LSB of the count value (i.e., each time the LSB digital block overflows, an interrupt is generated where the MSB gets incremented).
If the interrupt latency in the project is so high that the LSB digital block’s interrupt is not serviced before the LSB digital block generates the next interrupt, then one increment of the MSB byte variable is missed. This causes the ADC result to get corrupted.
Typically the interrupt latency in a project increases when large ISRs are called during interrupts.
So, to avoid this issue, reduce the size of the ISRs in the project. The size of ISRs can be reduced by performing only the operation of setting flags during interrupts, and performing the actual logic (which is intended to be performed during the interrupts) in the main application code after polling for the flags.
Note the following:
It may also be a good idea to place the digital blocks related to the ADC on the uppermost digital rows, since they have higher interrupt priority. Although this in itself may not eliminate the issue, it would be a good practice to do this, especially in a project containing several interrupt sources.
The reason is this: PSoC 1 does not have a nested interrupt feature. So, even if a single low-priority interrupt is executing a routine, all other higher-priority interrupts occurring after it have to wait (will be in pending). But, once that low-priority interrupt routine completes execution, the pending interrupt with the highest priority will execute. So, if you provide the ADC’s counter digital block as high a priority as possible (by placing it on the upper digital rows), it is more likely to reduce the interrupt latency for the ADC counter.
- PSoC 1 ADCs such as DelSig ADC and ADCINC, which use a hardware decimator for generating the ADC result from the analog modulator’s output bit stream, do not face this problem with interrupt latency, since the ADC result is calculated completely in the hardware (decimator) without intermittent firmware interruptions.