Number of cycles required to read CY7C1380 (standard Sync pipeline) | Cypress Semiconductor
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Number of cycles required to read CY7C1380 (standard Sync pipeline)
Is it possible to do an ARBITRARY NUMBER of CONSECUTIVE read access (one access per clock cycle) to a series of random locations; i.e. it is possible to use this chip to read the entire memory in 512K clock cycles?
Yes. The first access to the device will take two cycles, but every access after that will only take one. Therefore, the whole memory can be read in 512K + 1 clock cycles.