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NoBL Sram Definition | Cypress Semiconductor

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NoBL Sram Definition

Last Updated: June 18, 2011

What is a NoBL SRAM?


NoBL stands for No Bus Latency. NoBL devices are designed to be used in high performance systems on common I/O busses. NoBL SRAM's are capable of consecutive alternating reads/writes which are is possible with normal Synchronous SRAM's. This is achieved by eliminating idle cycles by making writes and reads symmetrical. NoBL SRAM's come in two flavors: Pipelined and Flow-through. Unlike normal Synchronous SRAM's where the write takes one clock cycle and read take 2/3 cycles depending upon Flow-through/Pipelined, the NoBL SRAM's take 2 clock cycles for writes and reads on a Flow-through and 3 clock cycles for writes and reads on a Pipelined NoBL SRAM.

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