necessity of clock when a ZZ pin is asserted | Cypress Semiconductor
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necessity of clock when a ZZ pin is asserted
According to the datasheet for a Sync SRAM device, the clock is still available to the device after the asynchronous ZZ signal is asserted. Is the clock necessary? Is it possible to stop applying the clock, by tying the clock to either "1" or "0", after asserting the ZZ signal?
The ZZ pin can only be asserted after disabling the chip, for which you would need the clock. So, the clock can be removed after 2 clock cycles of asserting the ZZ pin. The clock has to be supplied 2 clock cycles ahead in order to come out of the ZZ status.