Multi-Buffering of FX2LP endpoints | Cypress Semiconductor
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Multi-Buffering of FX2LP endpoints
Does multi-buffering of an endpoint FIFO increase the depth of the FIFO? Can you please provide further information on multiple buffering and the advantage of having an endpoint multi-buffered?
As far as the 8051 code is concerned there is NO difference in addressing an endpoint that is multi-buffered. Buffering only allows the 8051/external peripheral to access a buffer space while the other is in transition over USB. Endpoint buffering has no effect on increasing the depth of the FIFO. The depth of the FIFO still is 512/1024 bytes (as configured in EPxCFG register) and your firmware must not address an index greater than 511/1023 while filling the buffer. Internal logic will basically handle the ping-ponging of the buffers.
The CPU can only access the "active" buffer of a multiple-buffered endpoint. In other words, firmware must treat a quad-buffered 512-byte endpoint as being only 512 bytes wide, even though the quad-buffered endpoint actually occupies 2048 bytes of RAM."
For an IN transfer once the data is committed to the USB, the internal logic will assign the next 512 byte buffer as the "active buffer". This is all done by internal logic and is not visible to the 8051. The 8051 must treat the buffer as 512 bytes only. The external master must avoid writing to a full FIFO, or reading from an empty FIFO. The external master can use the FIFO full/empty flag to monitor the state of the FIFO and decide when to stop writing/reading from the FIFO.