Minimum Pulse Width for external Interrupt pins INT0# | Cypress Semiconductor
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Minimum Pulse Width for external Interrupt pins INT0#
Is there a minimum pulse width for INT0 when it is in "edge" mode?
The FX2LP having the standard 8051 behavior as far as the external interrupts are concerned have the same pulse width specified for the external interrupt pins: 4 clocks high, 4 clocks low.
The external interrupt when configured to be edge triggerred it will be triggered either on rising or falling edge as configured. Once triggered it will remain in the triggerred state (if set to falling edge it will remain low; if set to rising edge, it will remain high) until the INT flag is cleared by the 8051.