Meaning of bit 2 in register 0x05 of the SL811HS | Cypress Semiconductor
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Meaning of bit 2 in register 0x05 of the SL811HS
Question:In the Emb_host firmware and in the source code given by "SL811HS/SL811HST Application Notes" at page 27 register 0x05 is being written with 0x05, which means a reserved bit is being set, why?
The Control Register (address 0x05) is defined as shown below (see data sheets for more information):
|Bit||SL811HS - Host||SL811HS - Slave|
|0||SOF Enable||USB Enable|
|3||USB Engine Reset||J-K Force state bit 0|
|4||J-K state force||J-K Force state bit 1|
|5||USB Speed||Speed select|
In the referenced documents the writer was setting bit 2, but as can be seen in host mode this bit has no meaning. While the application note mentioned is from an obsolete development kit and is a good source of information, it should be used with caution because several errors have been found in it. It does not hurt to set the Reserved bit in Host mode but in practice it should be set to 0. Note that when operating in Slave mode this bit does have a meaning in regards to the DMA operation. Another thing to note is that the SL811HS errata mentions issues with regards to DMA operation so even in Slave mode DMA is not recommended.