Maximum ramp time allowed for voltage on input rail | Cypress Semiconductor
Support & Community
Maximum ramp time allowed for voltage on input rail
What is the maximum ramp time allowed for voltage on input rail?
In systems that have a DC input supply (to PowerPSoC) with ramp rates at 15V/ms or faster, a power supply sequencing scheme must be implemented to prevent potential damage to the load and other components in the system.
In the event of fast power supply ramp (faster than 15V/ms), or with small LED loads, the parasitic capacitances could cause the internal MOSFET to be in an ON state for short periods of time at system startup. This is because the PowerPSoC MOSFET is at an interface between the multiple power supply domains (GDVDD, HVDD), and the differences between these respective ramp rates is the potential reason for this condition.
For more information, please refer to the sub-section “Power Supply Sequencing” in Technical Reference Manual for the CY8CLED family. This TRM can be found in the Help >> Documentation menu inside PSoC Designer. The file name is TechnicalReferenceManual_CY8CLED04DXX.pdf.
The input power supply (HV domain) should not ramp to its final state faster than 1 μs.