You are here

Maximum number of cascaded FIFOs | Cypress Semiconductor

Support & Community

Maximum number of cascaded FIFOs

Last Updated: June 17, 2011

How many FIFOs can I cascade in depth and by width? What are the considerations?


The maximum number of FIFOs that can be cascaded depends on the type of FIFO and the arrangement of the expansion (by depth or width). With most synchronous FIFOs, the number of cascaded FIFOs (either by depth or by width) should not be greater than 6. It actually depends on how much capacitive load the driving device is able to drive. If the driver is not able to drive minimum 30pF, the number that can be cascaded will be less than 6. The reason for this is when the FIFOs are cascaded, all the shared inputs are tied together which increases the capacitive load. This will increase the rise and fall time of the signals and compromise the timing. Similarly, all the shared output signals of the FIFO's are tied together as well. Since each input pin has approximately 5pF input capacitance and each FIFO output is specified to be able to drive up to 30pF, no more than 6 devices should be cascaded. Otherwise, the rise and fall time of the signal will be affected, and thus the timing may be compromised. With depth expansion of FIFOs, there is no limit since the output of one FIFO goes into the input of the next FIFO down the chain; unlike the DeepSync FIFO's where all FIFO's cascaded together and share the same input and output buses. One thing to note, though, is that as the number of these FIFO's cascaded in depth increases, so does the latency of the first word to be available at the output of the last FIFO in the chain.

Knowledge Base Tags: 

Provide feedback on this article

Browse KB By Product

Browse KB by Type