You are here

Master Reset problems | Cypress Semiconductor

Support & Community

Master Reset problems

Last Updated: June 13, 2011

- What all things can affect Master Reset?
- Even after following timing specifications for Master Reset, it is not working , why ?
- Will noise on the signal lines affect the functionality of the device.


It is very important to do a full and complete Master Reset cycle upon powering up any FIFO. The parameters for a full reset are described in the datasheet for each respective FIFO. However, sometimes, even if the timing specifications are met, there is a problem with the reset cycle. This is usually caused by a noise pulse on the MRST line. This is an unintentional signal fluctuation that can corrupt the Master Reset cycle. This can be caused by interference from other signals, long traces, or any of a number of factors. If you suspect a noisy MRST line as being the cause of your problems, use an oscilloscope to check the signal. (A logic analyzer will not pick up on noise pulses)

Knowledge Base Tags: 

Provide feedback on this article

Browse KB By Product

Browse KB by Type