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Master Reset cycle | Cypress Semiconductor

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Master Reset cycle

Last Updated: June 23, 2011

- How to reset the FIFO?
- How to operate /MR?
- What is a proper reset?



The FIFOs need a proper Master Reset after turning on the power. A reset pulse

empties the device and sets the flags to represent the empty state. If a complete

and correct master reset cycle is not accomplished, the FIFO will not work properly.

The exact constraints of a reset cycle are defined in the datasheets. Usually there is

a minimum reset pulse which must be met. Giving the device a reset pulse includes

both an assertion and de-assertion edge to the reset pin. In addition, the read and

write enable signals for all FIFO's normally must be disabled during the reset pulse

except with some devices when programming the PAE and PAF flags. Also, one needs

to make sure that there is no noise pulse on the /MR signal when interfacing with

other devices. Any noise on reset may lead to an improper reset which may result in

some problems.

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