Limitations of STA tool in PSoC Creator | Cypress Semiconductor
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Limitations of STA tool in PSoC Creator
What are all the limitations of Static Timing Analysis tool in PSoC Creator
Static timing analysis tool only has the access to design during the build process, so it does not have knowledge of how the elements of the design will be used or of any changes made dynamically (such as firmware that changes a clock frequency). Because of these limitations, static timing analysis may find critical paths that are not real problems because of the way the design is used.
Static timing analysis does not have knowledge of how signals are generated or used outside the PSoC. It can display delays related to such signals, but cannot automatically find timing violations.