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Layout Recommendation for the SL811S | Cypress Semiconductor

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Layout Recommendation for the SL811S

Last Updated: September 03, 2009

Question: Do you have any layout recommendations for the SL811ST?

Response: At this time there isn't an application note or other collateral that gives any specific recommended layout guidlines for the SL811S. Since the SL811S is not a high speed device the layout requirements are pretty flexible. Below are some general USB layout guidelines for High speed devices (this is worst case, so full speed device layout can be simpler):

USB 2.0 PCB layout recommendations (as a starting point):

4 layer, impedance controlled boards are required.

Impedance targets must be specified (ask your board vendor what they can achieve).
Do not cross plane splits.

Minimize vias.

Maximize distance to other traces.

Control trace widths to obtain target impedance.

Maintain strict trace spacing control.

Minimize stubs.

Common mode chokes (2-wire, @100MHz should be < 300 ohms, differential impedance @100MHz should be < 8 ohms) are a proven USB 2.0 EMI solution.

Refer to the USB 2.0 design guideline for solutions that work for USB2.0 FS & HS signal quality requirements.

Proper grounding of chassis is crucial.

Connector shell must connect to green wire ground early and well.

Short D+/D- traces from connector to silicon.

I/O shield must connect securely to chassis and receptacle.

Bypass/flyback caps on VBus near connector (ESD strikes, "helper").

Refer to Chapter 7 of USB2.0 spec at

In addition, I would recommend reading the design guidelines document by USB-IF . You can find the USB-IF document at:

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