Jumper usage on the PLC evaluation and development kits | Cypress Semiconductor
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Jumper usage on the PLC evaluation and development kits
Describe the jumpers on the various PLC boards and explain their usage.
There are six jumpers on the CY3272 and CY3273 boards in the orientation as shown below.
CY3272 jumper layout
CY3273 jumper layout
- The PWR jumper is used to connect pin V on the I2C header to Vdd. This can be used to power a microcontroller board of the supply of the CY3272 or CY3273 board.
- The INT pin (it is not a true jumper) is the pin closest to the INT silk screen on the board. It is connected to the HOST_INT pin of the CY8CPLC10 chip. This pin can be used to connect to the host microcontroller interrupt pin to enable interrupt based processing. The polarity and status updates that trigger the interrupt can be controlled in the INT_ENABLE register (offset 0x00) in the memory map. The other part of the jumper is connected to GND and can be used to while probing the digital signals on the board.
- The RES jumper is used to connect pin R on the I2C header to XRES. If the host microcontroller board can reset the CY8CPLC10 chip by momentarily forcing this pin to Vdd.
- The SCL and SDA jumpers are used to pull up pins D [I2C data] and C [I2C clock] to Vdd. Note that for the CY3272 board, the jumpers have to be placed laterally as shown in Figure 1 above. These need not be connected to connect to boards such as the CY3240 USB-I2C bridge as it already has pull ups for I2C but should be there for boards such as the PSoCEval1.
- The CLK jumper is used to check the external clock frequency between P1  and P1 .
The CY3274 and CY3275 have only four out of the six jumpers present on the evaluation boards as shown in the figures below. The descriptions for these jumpers are similar to the ones above (XRES is similar to RES). Note that on the CY3274 and CY3276 the jumpers JP1 is for PWR, JP5 is for XRES, JP3 is for SCL and JP4 is for SDA.
CY3275 jumper layout
Figure4. CY3274 jumper layout