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Jitter performance in CY23020-1 or CY23020-3 | Cypress Semiconductor

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Jitter performance in CY23020-1 or CY23020-3

Last Updated: June 23, 2011

How can I obtain a minimum jitter performance from the CY23020-1 or CY23020-3 component?


Both versions of the CY23020 device, single ended and differential, have a PLL bypass mode. If you do not need to use the delay adjusting feature of the device you can put it into its bypass mode by setting S1 = 1 and S2 = 0. In this mode, the jitter will be dramatically reduced. Another thing that will occur is that overall power consumption will be reduced because the internal circuitry that composes the PLL portion of the device will be powered down. This is a good method of creating a large quantity of low clock-to-clock skew signals when their delay from the source clock is not an issue.

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