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I/O System Restrictions in the PSoC® 4000 Family – KBA91258 | Cypress Semiconductor

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I/O System Restrictions in the PSoC® 4000 Family – KBA91258

Last Updated: August 20, 2015

How is the PSoC® 4000 I/O system different from the rest of the PSoC 4 family? What are the restrictions on the pin usages? 


The PSoC 4000 family, being the smallest member of the PSoC 4 architecture, has a scaled-down I/O and routing system compared to the larger members of the family. The Digital System Interconnect (DSI) is absent in the PSoC 4000 family, leaving the pin routing completely to the High Speed Input/Output Matrix (HSIOM). Because of this, hardware resources available in the device have dedicated pins for input/output signals. 

In addition to the scaled down I/O and routing system, the family supports a separate VDDIO power domain on three I/Os in the 16-pin QFN package. This VDDIO domain is absent in the 4100/4200 families. Refer to the “Power” section in the PSoC® 4: PSoC 4000 Family Datasheet for more details.

This knowledge base will only cover the restrictions on the I/Os. For complete details on the I/O system, refer to Chapter 7, “I/O System” in the PSoC 4000 Family Technical Reference Manual.

Restrictions on the pins:

CapSense® pins:

Not all the pins available in the device are CapSense I/O compatible. The Port 3 pins (P3[0], P3[1], and P3[2]) cannot be used for CapSense sensing or shielding purposes. For example, out of the 20 possible I/Os in the 24 QFN device, only 17 I/Os are CapSense compatible. Table 1 lists the CapSense compatible I/Os and their availability in the different packages.


Table 1. CapSense I/O Compatibility Across Packages


Dedicated pins:

The Timer Counter Pulse Width Modulator (TCPWM) block, Serial Communication Block (SCB) and Comparator output have dedicated pins for input and output routing (except the Comparator input which can connect to the Analog Mux bus and then to any CapSense compatible I/O). Refer to Table 1 in the “Pinouts” section of the PSoC® 4: PSoC 4000 Family Datasheet for the available pin options. Table 2 shows a snapshot of the table for quick reference. 


Table 2. PSoC 4000 Pin Descriptions


Special functionality of P1[6]

In all the devices in the PSoC 4000 family, P1[6] is temporarily configured as the XRES pin during power-up for approximately 100 ms, until the device enters the start-up code. Care should be taken when using this pin. P1[6] SHOULD NOT BE PULLED DOWN DURING POWER-UP (for example, connecting active-high LEDs) because the device will enter and remain in the XRES state after power-up, as the reset signal is always asserted.

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