IO pins usage when a Synchronous SRAM in interfaced with an FPGA | Cypress Semiconductor
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IO pins usage when a Synchronous SRAM in interfaced with an FPGA
When CY7C1380D interfaced with an FPGA and is/are running short on IO pins. Can we do the following?
Can we apply burst addresses out of the FPGA with the auto increment burst operation?
Can we use nBWa,b,c,d with nBWE permanently on GND to mask writes?
Can we have nADV, nADSP and nADSC permanently asserted?
1. This auto increment burst from FPGA won’t work if burst operation is required in the SRAM.
For SRAM burst, ADV/ pin should be asserted low and the Mode pin should be selected accordingly for linear or interleaved burst.(Needs to be modified)
2. The BWS/ (a,b,c,d) are used for selecting the bytes to which data needs to be written.
If writes need to be masked. BWS/ should be asserted HIGH (disabled) and GW/ should be HIGH.
3. Yes, it is possible to have ADSP/ and ADSC/ permanently asserted. ADV/ if asserted low always will set the SRAM in burst mode.