Interfacing SRAM JTAG Signals Using a Voltage Level-Shifter - KBA81536 | Cypress Semiconductor
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Interfacing SRAM JTAG Signals Using a Voltage Level-Shifter - KBA81536
How do I interface SRAM JTAG signals across devices on multiple voltage domains?
Use a voltage level-shifter IC that provides CMOS rail-to-rail output signal. Avoid the use of level-shifter IC with open drain output.
Extended Response: System boards generally contain integrated circuit (IC) devices that run on multiple voltage domains (e.g. 3.3 V, 1.8 V, 1.2 V, and so on). The Cypress synchronous memory device JTAG TAP module is fully compliant with the IEEE 1149.1 standard and comes in two types:
- QDR SRAM: Complies with JEDEC-standard 1.8 V I/O logic levels.
- Sync/NoBL: Complies with JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
Connecting these memory devices with other devices through a common JTAG boundary scan chain as well as providing a common TCK clock requires either a step up or a step down in signal voltage level. Most often, this is done with a discrete voltage level-shifting IC. Figure 1 shows TCK/TDI/TDO signals connected across several ASIC/FPGA and SRAM devices via the level-shifting IC.Figure 1: JTAG Scan Chain with Devices on Different Voltage Domains
The choice of level-shifting IC determines the rise and fall time of the signal reaching the next device in the scan chain. Cypress SRAM device’s JTAG I/O buffers are designed to work with strong signal slew rate and the presence of level-shifting ICs in the path can adversely affect quality of incoming signal. As a best practice, avoid use of level-shifting ICs with open-drain output. This type of level-shifter requires a resistive pull-up to achieve output high voltage (VOH). The slew rate of signal from level-shifting IC going to the memory device depends on the value of the pull-up resistor; the higher the resistor value, the lower the slew rate and vice-versa. Figure 2 shows the output waveform from this type of level-shifter.
In case of TCK clock, slower signal rise time coupled with signal noise or VCC/GND bounce can give rise to false clocks inside the memory device. Input buffers tend to be immune to signal noise for sufficiently fast signal ramp rate. For slow rising signals, the noise can cause the input buffers to trigger false transitions inside the device as demonstrated by Figure 3.
Case1: TCK Signal with No Noise and Fast Ramp
Case 2: TCK Signal with Noise and Fast Ramp
Case 3: TCK Signal with No Noise and Slow Ramp
Case 4: TCK Signal with Noise and Slow Ramp
In Figure 3, Case1 and Case2 represent TCK signal with and without noise for a fast rising signal. The trip period is shortest when there is zero noise and is relatively small with a small amount of noise in the signal. Input buffers tolerate some amount of noise with relatively small trip period. Case3 and Case 4 represent TCK signal with and without noise for a slow rising signal. The input buffer for a slow rising signal may be able to reliably sample the input signal assuming there is zero noise on the input signal. However, this is not realistic as all systems induce some noise in the signal. The signal will stay at the trip point for much longer duration, generating one or more false transitions internally. The same effect is seen on TMS/TDI input signal or output signal from TDO going to the next device in the scan chain. If the open-drain output level-shifting IC is already built into the system, the problem of false clock/signal trigger can be mitigated by use of a smaller resistor value at the expense of a slightly higher VOL signal from the level-shifting IC. Identification of the optimal value requires experimentation with various pull-up resistor values. Cypress recommends the use of level-shifting ICs that provide CMOS rail-to-rail output. This produces a strongly driven VOH/ VOL signal from the level-shifting IC to and from the memory device. We also recommend maintaining the signal rise and fall time equal to or better than 1 V/ns. Figure 4 shows the output waveform for this type of level-shifter.