You are here

Interfacing FX2LP™ with Image Sensor - KBA95736 | Cypress Semiconductor

Support & Community

Interfacing FX2LP™ with Image Sensor - KBA95736

Last Updated: January 30, 2015

The Hi-Speed USB controller FX2LP CY7C68013A can be used for image sensor applications (in vendor mode) as shown in Figure 1.

Figure 1. FX2LP Interface with Image Sensor


FX2LP Pin Descriptions:

  • CLKOUT: FX2LP can provide a 12-MHz, 24-MHz or 48-MHz.clock to the image sensor. Using FX2LP as the clock source you can avoid using an extra clock source for image sensor.
  • IFCLK: Data transfers on FD are synchronous with IFCLK.
  • SLWR:When FX2LP is used in slave FIFO mode, SLWR has to be asserted to write data to endpoint buffers.
  • PA0: This GPIO can be used to monitor the start/end of the frame. You can either use PA0 as a normal GPIO or as an interrupt pin for monitoring VSYNC.
  • FD[7:0]: Port B of FX2LP has to be used as 8-bit parallel interface. If the image sensor has data lines >8 (<16), it is better to connect the upper eight data lines and leave the lower data lines of the image sensor as floating. If you want to use all the data lines >8(<16), then use both port B and Port D as 16-bit parallel bit interface. In this case, FX2LP will pass two bytes of information for each pixel adding some extra redundant bits (if number of data lines > 8 (<16)) .The host application must filter out the bits that are not related to the pixel.
  • I2C: FX2LP can act as an I2C master. You can configure image sensor registers using the I2C interface.

Image Sensor Pin Descriptions

  • XCLK: Input pin for clock. If the image sensor doesn’t support the 12-MHz, 24-MHz, or 48-MHz clock, an external clock source must be used.
  • PIXCLK: The image sensor data is synchronous to PIXCLK and must be connected to IFCLK of FX2LP.The frequency of PXICLK should be in between 5-48 MHz
  • VYSNC: The frame valid signal that indicates the starting and ending of the frame.
  • HSYNC: The line valid signal that indicates that there is valid data on data lines.
  • D[7:0]: Output data lines that carry the image data.
  • FIFOADR0 and FIFOADR1 pins of FX2LP must be connected to logic HIGH or logic LOW per the endpoint buffer that is used.

The following flowcharts provide an overview of the application:

Host Application Flowchart

Host Application

FX2LP Project Flowchart

FX2LP project

Note: 1 and 2 indicated in this flowchart are just reference points.

Note: FX2LP does not support UVC class that requires header and footer for each frame. The 8051 CPU is not fast enough to insert header and footer in between frames. Therefore, if you want to implement UVC class with FX2LP, an external FPGA must be used. The FPGA must insert the header and footer in between frames and pass the data to the FX2LP.

Create a tech support case to obtain an example project.

Knowledge Base Tags: 

Provide feedback on this article

Browse KB By Product

Browse KB by Type