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Interfacing an FPGA to the CY7C68000 TX2

Last Updated: April 04, 2011

Does Cypress provide RTL code for creation of an SIE to be used with the Cypress CY7C68000 TX2 PHY chip?



Unfortunately we do not provide VHDL or Verilog code for creating the SIE logic that interfaces with the CY7C68000 transceiver. This is not a trivial task, and is usually undertaken by peripheral IP vendors such as Mentor graphics, Synopsys, etc., or ASIC vendors who want further integration. The assumption is that the USB 2.0 specification and UTMI specification are well understood.

Mentor graphics has a USB 2.0 VHDL core (MUSBHSFC):

Synopsys also has a USB 2.0 core:

The SIE logic should be designed to the UTMI spec version 1.05, which can be downloaded at:

A alternative part selection for you may be the CY7C68013A FX2LP or CY7C68001 SX2. The SIE logic is integrated into the USB core with these parts, and the FPGA can master the FX2LP or SX2 through the Slave FIFO interface for exchanging payload data with the host.

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